Error about Incompatible IOBs Are Locked to the Same Bank

[lyh8]

I use Xilinx ISE Project Navigator v12.1 to modify an old FPGA project. After adding several new signals, I ran the Implement Design, and I got several errors of the same type as below

Place:864 - Incompatible IOB's are locked to the same bank 1
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
List of locked IOB's:
dac_sdata
dac_pre_n
dac_load_n
dac_cs_n
dac_mode
dac_sclk
IO Standard 2: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
List of locked IOB's:
rdc2_sample_n
rdc2_cs_n
rdc2_rd_n
rdc2_en
rdc2_rdvel_n
rdc2_soe_n
These IO Standards are incompatible due to VCCO mismatch.

Please advise what was wrong. Thank you in advance.

[lzmind]

Hi lyh8, the error message basically tells you that you have two sets of signals that are sourced differently to 3.3V and 2.5V, and locked in one bank, which is not allowed.
If you really need to have rdc2_xx signals sourced to 2.5V, you must assign the signals to a separate bank.
If the signals rdc2_xx also belong to 3.3V, then you must have forgotten the pin configurations. If this is the case, you shall use the I/O Pin Planning (PlanAhead) tool to set the I/O standard. By default, the I/O standard is set to 2.5V. You need to change it to LVCMOS33 which means 3.3V for each pin. Then, those signals can be assigned to the same bank as other signals.

Hope that helps.

[lyh8]

I confirm that assigning pins to LVCMOS33 corrected the error. I appreciate your advice, which really helps.

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